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1
Pin Connections
16 15 14 13
V REGA 1
V SS 2
V REG 3
V SS 4
17
12 CS
11 MOSI
10 SCLK
9 V CC
5
6
7
8
Figure 5. Top View, 16-Pin QFN Package
Table 2. Pin Descriptions
Pin
1
2
3
4
Pin
Name
V REGA
V SS
V REG
V SS
Formal Name
Analog
Supply
Digital GND
Digital
Supply
Digital GND
Definition
This pin is connected to the power supply for the internal analog circuitry. An external capacitor must be
connected between this pin and V SSA . Reference Figure 1 .
This pin is the power supply return node for the digital circuitry.
This pin is connected to the power supply for the internal digital circuitry. An external capacitor must be
connected between this pin and V SS . Reference Figure 1 .
This pin is the power supply return node for the digital circuitry.
The function of this pin is configurable via the DEVCFG register as described in Section 3.1.6.6 . When the
5
ARM_Y/
PCM_Y
Y-Axis
Arm Output /
PCM Output
arming output is selected, ARM_Y can be configured as an open drain, active low output with a pullup current;
or an open drain, active high output with a pulldown current. Alternatively, this pin can be configured as a
digital output with PCM signal proportional to the Y axis acceleration data. Reference Section 3.8.10 and
Section 3.8.11 . If unused, this pin must be left unconnected.
The function of this pin is configurable via the DEVCFG register as described in Section 3.1.6.6 . When the
6
ARM_X/
PCM_X
X-Axis
Arm Output /
PCM Output
arming output is selected, ARM_X can be configured as an open drain, active low output with a pullup current;
or an open drain, active high output with a pulldown current. Alternatively, this pin can be configured as a
digital output with a PCM signal proportional to the X-axis acceleration data. Reference Section 3.8.10 and
Section 3.8.11 . If unused, this pin must be left unconnected.
7
8
9
10
11
12
13
14
15
16
17
TEST /
V PP
MISO
V CC
SCLK
MOSI
CS
V SSA
NC
NC
V SSA
PAD
Programming
Voltage
SPI Data Out
Supply
SPI Clock
SPI Data In
Chip Select
Analog GND
No Connect
No Connect
Analog GND
Die Attach
Pad
This pin provides the power for factory programming of the OTP registers. This pin must be connected to V SS
in the application.
This pin functions as the serial data output for the SPI port.
This pin supplies power to the device. An external capacitor must be connected between this pin and V SS .
Reference Figure 1 .
This input pin provides the serial clock to the SPI port. An internal pulldown device is connected to this pin.
This pin functions as the serial data input to the SPI port. An internal pulldown device is connected to this pin.
This input pin provides the chip select for the SPI port. An internal pullup device is connected to this pin.
This pin is the power supply return node for analog circuitry.
Not internally connected. This pin can be unconnected or connected to V SS in the application.
Not internally connected. This pin can be unconnected or connected to V SS in the application.
This pin is the power supply return node for analog circuitry.
This pin is the die attach flag, and is internally connected to V SS . Reference Section 5 for die attach pad
connection details.
Corner Pads
The corner pads are internally connected to V SS .
MMA65xx
Sensor
4
Freescale Semiconductor, Inc.
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